Power grid design and signoff for high speed CPU core.
- 4-10 yrs experience in Physical Design and power grid design analysis for high speed cores.
- Should have good exposure to high frequency design convergence for PDN and descent exposure to physical design methodology.
- Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 4+ years of experience in IC design.
- Experience in leading block level or chip level Physical Design and PDN activities.
- Work independently in the areas of RTL to GDSII implementation.
- Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
- Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
- Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
- Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.
- Strong problem-solving skills.
- Bachelors – Computer Science, Bachelors – Engineering, Bachelors – Information Systems
- 4+ years Hardware Engineering experience or related work experience.